This invention relates to a method for forming a multi-chip integrated circuit package.
Conventional multi-chip packages require a bulky substrate to provide connections between the integrated circuits (ICs) of the package and also to provide the pins or solder elements that facilitate connection of the package to a printed circuit board (PCB). The substrate can also support any required passive components. The integrated circuits can be electrically connected to the substrate and passive components using wire bonding, flip chip attach, or solder mount techniques. Once the components of the package are in place and the electrical connections have been formed, the assembly then requires overmolding with an insulating material in order to protect the ICs, passive components and the interconnects from damage.
Such multi-chip packages have two main problems. Firstly, the size of the package formed is generally large, and secondly, the use of component-level processing in the formation of the package is generally expensive in terms of the manufacturing cost.
Several techniques have been proposed that allow the production of smaller semiconductor packages, although many are not suitable for producing multi-chip packages with which the present invention is concerned. One method that allows the formation of compact semiconductor packages is the “flip chip” technique described in U.S. Pat. No. 6,287,893, which is used to form integrated circuit chips that have contact pads bearing solder bumps for attachment to a patterned substrate. This is achieved through the use of a redistribution layer that maps connections of the integrated circuit to an array of solder bump pads. Such “flip chips” are compact and can be encapsulated to form a semiconductor package using conventional packaging techniques.
Another method that allows the formation of compact semiconductor packages is described in reissued U.S. Pat. No. RE38,961. The patent describes a method for forming contact bumps directly onto the integrated circuits of a semiconductor wafer, encapsulating the circuit-forming surface of the wafer with a sealant by screen printing and then mechanically grinding away the surface of the sealant until the upper ends of the bumps are exposed. The use of screen printing allows equipment costs to be reduced as compared with previous methods described in the art that use a mould in order to form the sealant layer.
However, these patents do not provide methods for forming multi-chip packages and do not solve the problem of requiring a bulky substrate for supporting the multiple ICs.
There is therefore a need for inexpensive method for forming chip package that comprises multiple integrated circuits.